1. Field of the Invention
The present invention relates generally to the field of semiconductor devices and more particularly to the packaging of semiconductor devices.
2. Background Art
III-nitride power devices such as Gallium Nitride high electron mobility transistors or GaN HEMTs are known in the art for high power performance. However, the performance of such devices has been constrained by the use of conventional interconnect schemes. Thus, GaN HEMT devices utilizing multiple interconnect metal layers have been developed in the art.
Such multi-level III-nitride power devices have used conventional integration methods, such as solder ball arrays, for integration onto a support surface such as a printed circuit board. In particular, when integrating reduced footprint packages, it is often expedient to use solder ball arrays to prevent problems such as solder bridging. Unfortunately, such conventional integration methods increase the Rdson, or the “on resistance,” of the device by limiting the flow of current through the circuit, thereby negating the advantages of using multi-level III-nitride power devices in the first instance.
Thus, a solution is needed for integrating multi-level III-nitride power devices onto support surfaces while reducing Rdson, thereby leveraging the high power performance capabilities of III-nitride power devices.